PC-1 - UNIVERSITY OF TOKYO - TOKYO, JAPAN
The PC-1 is a pilot model, binary,
single-address computer installed at Department of Physics, Faculty of
Science, University of Tokyo, and one of the first general purpose
computers using parametron logic and two frequency magnetic core
memory. Its construction was started in September 1957 and completed
in March 1958. Its successful operation and high performance have lead
to the construction of several larger computers based on the same
design principle. Standard machine running hours are from 9:00 a.m. to
9:00 p.m. from Monday to Saturday. It is primarily intended for
exploratory work on logical design and programming of computers, but
about half of the time is made available to other laboratories in the
university.
Memory. Magnetic core memory of the
PC-1 uses sinusoidal waves rather than pulses for write-read
operation. The core matrix consists of a 36 x 256 rectangular wire
net. In each writing operation, a sinusoidal wave of frequency f/2 is
put through the selected one of the 256 "row" wires, and the 36
information bits are applied to the 36 "column" wires in the form of
the sinusoidal wave of frequency f, where the sign or phase of the
latter wave represents each information bit. The core on the cross
points of both wires are subjected to the magnetizing force of the
form I0 cos π ft ± I1 cos 2π ft,
and the asymmetry of this wave form causes magnetization of the core
in one or other direction.
The read-out of information is achieved by
applying the current of frequency f/2 on a row wire and picking up the
2nd harmonic from the column wires.
The current of frequency f/2 is generated by
special parametron elements used as frequency dividers. The selection
of a particular row out of 256 is made by the threshold action of these
parametrons against variation of the exciting current. The exciting
inputs to these parametron frequency dividers are derived from a
special multi-winding transformer called "polyhybrid." Each of its
output winding forms 256 different types of linear superposition of
the outputs of 18 power amplifiers, and the phases of these power
amplifiers are changed in a definite way according to the bits
specifying the particular address. In this manner, one and only one of
the 256 parametrons receives a high input current, and all remaining
parametrons receive current not more than 1/3 of the maximum
value. This system, which is based on the same principle as the
error-correcting code, has the advantage that the machine operates
correctly even in case of failure of 1 or 2 tubes in the power
amplifier, and has proved superior both in economy and
reliability.
Control. The design of the whole
computer is based on synchronous philosophy. Control of the PC-1 is
characterized by overlapping operation of different stages of
successive instructions. The standard control sequence starts with the
end pulse of the previous instruction (i - 1). This causes reading of
the operand of the next instruction (i), and decoding of the same
instruction (i). At the end of the decoding operation, the operation
pulse is emitted, which causes execution of the operation of the
instruction (i), reading of the instruction (i + 1), and increasing
the content of the sequence counter to i + 2. There are, of course,
some exceptions in case of store instruction and other non-arithmetic
operations. These overlapping operations have been very effective in
increasing the speed of devices using perfectly synchronous circuit
elements such as parametron.
Arithmetic unit. The arithmetic unit
contains three 36-bit registers, A, R, and M. A and R are shifting
registers and form a double length register for some arithmetic
operations. A has a parallel adder used in all kinds of arithmetic and
logical operations. The adder has a special high-speed carry network
which enables the complete assimilation of carries in 36-bit addition
in only 6 logical stages.
Overlapping input-output operation. Standard
6-unit teleprinter equipments (similar to Flexowriter) are used for input
and output, together with a photoelectric tape reader. Since conversion
to and from decimal scale is always done by program, special provision has
been made to enable effective overlapping operation of input-output devices
and the computer. The address part of every input-output instruction is a
jump address, and when a particular input (or output) instruction is
encountered and the input (output) device is not ready at the moment
it is called for, the machine does not wait, but a jump takes place to that
address. When any of these devices becomes ready, the normal program
sequence is interrupted and control jumps to the address 511, while the
address of the instruction which was to be executed net if the break-in
did not occur is stored in the location 510. A special input-output
executive program can take care of an effective overlapping operation of
machine control and input-output devices by taking advantage of these
facilities.
Summary Specifications. 4200 parametrons;
number word, binary 18 bits (short word) or 36 bits (long word); instruction
word, binary 18 bits single address, 27 different instructions;
memory, magnetic cores, 512 short words; operation speed: addition and
subtraction 270 microsecond; multiplication 2970, store 540, unconditional
jump 270, negative jump 540; power consumption, 3kva; floor area, 8 square
meters.